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CDC 7600 – Research File

Summary in one paragraph

The Control Data Corporation 7600 was Seymour Cray’s deeply pipelined follow-on to the CDC 6600. It was designed at Chippewa Falls between 1965 and 1968, started life under the internal designation CDC 6800, and was renamed to 7600 around 1967 when Cray decided he could not maintain object-code compatibility with the 6600 without sacrificing the performance he wanted. CDC announced the machine publicly on 3 December 1968, the first system was delivered to Lawrence Livermore National Laboratory in January 1969 as serial #1 (cost $5.1 million; LLNL retained it until October 1988), and about 75 systems were eventually built worldwide through the early 1970s. The 7600 was the world’s fastest commercial computer from roughly 1969 to 1975. It ran on a 27.5-nanosecond clock (36.4 MHz), peaked at about 36 MFLOPS with 10-15 MFLOPS sustained, and was generally about ten times faster than the 6600. Its central architectural innovations were two: deep pipelining of nine functional units (the canonical “first deeply pipelined scientific computer”), and a two-level main-memory hierarchy – 65 536-word Small Core Memory (SCM) at 275 ns cycle and 512 000-word Large Core Memory (LCM) at 1760 ns cycle, software-managed, the precursor to modern caches. The system used about 5 000 cordwood modules, six PCBs each, of high-speed discrete silicon transistors (not yet ECL ICs), all packed into a “C”-shaped (not Y-shaped) cabinet redesigned by Dean Roush around freon-water heat exchangers, occupying about 6 by 10 feet at 188 cm tall and drawing 95 kW at 208 V 400 Hz. The 7600 was the bridge between the 6600 (parallel functional units, 1964) and the Cray-1 (vector pipelines, 1976). Its memory hierarchy looked forward to caches; its software-managed staging looked backward to a model that the Cray-1 would explicitly reject in favour of a single fast memory plus vector registers.

Naming history – 6800 to 7600

The 7600 was originally designated the CDC 6800. The name change occurred during 1967 when Cray determined that the design’s instruction set could not be made fully object-code compatible with the 6400/6500/6600 family without sacrificing the performance gains he was after. The design retained 60-bit word format, the same general register architecture (X, A, B), and broadly the same instruction style as the 6600 – but the I/O architecture was substantially different (15 dedicated I/O channels rather than the 6600’s PPU-via-data-channel scheme), the LCM/SCM split required new instructions, and the pipelined execution model had different timing properties.

The CDC 7600 official “Preliminary System Description” of November 1968 makes the compatibility status explicit:

“The 7600 system is designed to be machine code upward compatible with the 6400/6500/6600 systems in the area of central processor routines; it is not compatible on the machine code level in the area of system programs or input-output drivers. The 7600 system input-output provisions have been generalized and greatly expanded over those provided in the 6400/6500/6600 systems.”1

That is, CPU-level user code was upward compatible (a 6600 FORTRAN program would generally compile and run), but system-level code – operating system, drivers, I/O code – was not, because the I/O architecture, the SCM/LCM model, and several control instructions had changed. This partial-compatibility break is what apparently prompted the renaming. Wikipedia’s CDC 7600 article puts it as: “It had originally been named the CDC 6800, but was changed to 7600 when Cray decided that it could not be completely compatible.” [Wikipedia: CDC 7600.]

The Ed Thelen comp-hist comparison page notes the partial compatibility succinctly:

“Code compatible with CDC 6600 main processor. Extensive pipelining within the functional units permitted even more than a 4x speed increase over the 6600. … Different packaging approach – smaller and more compact design. More peripheral units were standard, used somewhat differently.”2

And HandWiki:

“Although the 7600 shared many features of the 6600, including hardware, instructions, and its 60-bit word size, it was not object-code compatible with the CDC 6600.”3

Date of rename: secondary sources are not precise. The transition is variously placed in “1967” (during the redesign that culminated in the 1968 announcement). HandWiki and Wikipedia both place the original 6800 designation in the 1965-1967 design period at Chippewa Falls.

Confidence: HIGH that the rename happened; HIGH that the reason was the compatibility break; MEDIUM on the precise month/year (most sources just say “during the design phase” or “1967”).

Dates

Announcement: 3 December 1968

The Computer History Museum’s This Day in History entry records:

“December 3, 1968: CDC Announces 7600 Supercomputer.”4

The Computinghistory.org.uk entry corroborates: “3rd December 1968” announcement, “delivered in January 1969 to Lawrence Livermore National Laboratory and cost in the region of $5 million.”5 The CDC Preliminary System Description bears the date “November, 1968” – the document was produced for the December 1968 announcement.

Note: some derivative secondary sources (including Wikipedia’s infobox under “release”) cite “June 1967” as a release date. This appears to refer to the internal project go-ahead or perhaps an early CDC sales-collateral date for the initial CDC 6800 designation – it is not the public announcement of the 7600. The canonical public-announcement date is 3 December 1968, well attested by the Computer History Museum and contemporary secondary sources.

First customer ship: January 1969 – LLNL serial #1

The first CDC 7600, serial number 1, was delivered to Lawrence Livermore National Laboratory in January 1969 for $5.1 million. The placard affixed to the surviving CPU chassis at the Computer History Museum (catalog X1385.97U) reads verbatim:

“CDC 7600 S/N 1 – Delivered 01/69 retired 10/88 Cost: $5.1 million – 36 million operations per second – 4,000,000 bytes (chars) magnetic core memory – Small core memory: 65,000 60-bit words – Large core memory: 512,000 60-bit words – 3,360 modules – 120 miles of wire.”6

This is the canonical primary-source document for the LLNL serial-#1 specifications, the cost, the delivery date (January 1969), and the retirement date (October 1988 – nearly twenty years of service).

LLNL’s own published 1969 retrospective describes the arrival:

“Always eager for better computer simulations, Laboratory weapons designers enthusiastically greeted the arrival of their first CDC 7600 supercomputer in 1969. … Cray’s design team then further refined this approach, yielding the even larger and faster CDC 7600 in 1969. In the hands of Laboratory users, these machines defined scientific supercomputing for a decade.”7

LLNL retired the machine when it accepted the world’s first CRAY-2 in 1985, although the LLNL 7600 itself was kept in operation alongside the new Cray-2 for several years; the formal retirement date of October 1988 comes from the CHM placard.

Production end and last shipments

CDC 7600 production ran from 1969 through approximately the mid-1970s. The Wikipedia article and the IT History Society database both cite about 75 units built worldwide. A 1978 Science magazine reference cited by Wikipedia gives the number as 75 7600s. (Other secondary sources quote lower figures like 40 or 50; the 75 figure has the better primary-source provenance via the 1978 Science reference.)

The Cyber 76 (announced ~1971) and Cyber 175/176 (announced ~1973) were rebadged or evolved 7600 derivatives in the CDC Cyber product line, using the same eight-board cordwood module design and the same 27.5 ns clock period (per HandWiki). These are sometimes counted in the same production lineage.

Approximate production timeline:

  • Announced December 1968
  • First ship January 1969 (LLNL)
  • Peak shipping rate 1970-1973 (NCAR May 1971, CERN March 1972, etc.)
  • Production wound down through the mid-1970s; the related Cyber 76/175 products kept the architectural lineage alive into the late 1970s.
  • Total units: ~75 worldwide (canonical figure).

Confidence: HIGH on announcement, first-ship dates, LLNL retirement date. MEDIUM on the 75-unit figure (cited in Science 1978; some secondary sources give 40 or 50, but 75 is well-attested). LOW on a precise production-end date.

Performance

Headline numbers

  • Clock cycle: 27.5 ns minor cycle = 36.4 MHz nominal.8 The CDC Preliminary System Description specifies “27.5 nanosecond clock period” repeatedly; “synchronous internal logic with 27.5 nanosecond clock period.”9
  • Major cycle: 275 ns (10 minor cycles).
  • Peak compute: 36 MFLOPS (or ~36.4 MFLOPS).10
  • Sustained: about 10-15 MFLOPS on hand-compiled scientific code, “about 10 MFLOPS on hand-compiled code” being the canonical Wikipedia figure.
  • Speedup over 6600: about 5x to 10x, “generally about ten times as fast as the CDC 6600” (Wikipedia). The comparison depends heavily on workload: for code that exploited the deeper pipelines, the speedup could approach ten; for older 6600-style code that only used the SCM and didn’t keep the pipelines fed, the speedup was closer to four to five (the brochure quotes “Central processor computation exceeds four times as fast as corresponding computation in the 6600 system”).11 The CERN courier quotes a “factor of five” for the institution’s CERN comparison, while NCAR’s CISL says “the machine operated five times the speed of the CDC 6600” with reference to NCAR’s actual production workload.
  • Compared to 6600: 6600 ran a 100 ns clock at peak ~3 MFLOPS / sustained ~0.5-1 MFLOPS. 7600 was ~3.6x faster on raw clock, plus pipelining, for an effective ~10x.

Sustained vs peak

The 27.5 ns clock and roughly one instruction per minor cycle gives a peak rate of 36.4 million instructions per second; with effectively two floating-point operations per instruction in some pipeline configurations, the peak floating-point rate is the canonical 36 MFLOPS. The HandWiki entry quotes “15 MIPS” as a more typical sustained rate.

Reliability

A consistent secondary-source theme: the 7600 had serious early reliability problems. NCAR’s CISL records that “Its low mean-time-to-failure forced the CF [Computing Facility] to put extremely good job- and file-recovery procedures into the system.”12 Wikipedia and HandWiki both record that “both LLNL and NCAR reported the machine would break down at least once a day, often 4 or 5 times.” The CERN Document Server entry on the surviving 7600 module records that the machine had “a bad ground-loop problem causing intermittent faults and eventually requiring all modules to be fitted with sheathed rubber bands.”13

These reliability issues plagued installation acceptance and pushed customers toward sophisticated checkpoint-restart software (LLNL’s LTSS being the canonical example).

Architecture

Word, registers, instruction format

The 7600 retained the 6600’s basic register architecture:

  • 60-bit word.14
  • 24 user-visible registers in three classes (per the brochure):
    • 8 X-registers: 60-bit operand registers
    • 8 A-registers: 18-bit address registers (loading A1-A5 triggers automatic load to corresponding X; A6/A7 trigger store)
    • 8 B-registers: 18-bit index/scratchpad registers
  • 15-bit and 30-bit instructions, packed up to four per 60-bit word (the 7600 simplified the 6600’s instruction-issue rule: “the 7600 could issue one instruction per cycle regardless of instruction length,” whereas the 6600 took two cycles to issue a 30-bit instruction).15
  • Approximately 72-74 operation codes, with two basic addressing modes (register+register and register+immediate). Like the 6600, the 7600 is a load-store architecture with arithmetic strictly on registers.

Functional units – nine, deeply pipelined

The 7600 has nine functional units in the central processor, identified in the 1968 brochure schematic (Figure 2: “CPU Computation Section”). The list:

  1. Long Add – 60-bit fixed-point integer addition
  2. Floating Add – 60-bit floating-point addition/subtraction
  3. Floating Multiply – 60-bit floating-point multiplication
  4. Floating Divide – 60-bit floating-point division
  5. Boolean – bitwise AND, OR, XOR
  6. Shift – bit shift, rotate
  7. Normalize – floating-point normalization (separate from add)
  8. Population Count – count of one-bits in a word (the same NSA-requested instruction as on the 6600)
  9. Increment – 18-bit fixed-point operations on address registers

(The Branch unit in the 6600 is not a separate functional unit on the 7600 – branches are handled in control logic associated with the CIW (Current Instruction Word) register rather than as a pipelined arithmetic unit.16 Several secondary sources still count “Branch” as a functional unit, bringing the total to ten; the 1968 brochure schematic shows nine.)

Pipeline stages per functional unit (from the Edinburgh comp-arch reference):

Functional unit Pipeline stages Notes
Boolean 2 stages Two minor cycles (55 ns)
Long Add (fixed add) 2 stages  
Shift 2 stages  
Increment 2 stages  
Population Count 2 stages  
Floating Add 4 stages 4 minor cycles (110 ns) latency, same as 6600’s add unit
Floating Multiply 5 minor cycles (137.5 ns) Two-pass mode: “the equivalent of only one of these half multipliers, and this is used twice in a two-pass mode”17
Floating Divide 20 minor cycles, not pipelined “a repeated subtract and test algorithm which cannot be pipelined”
Normalize 3 stages  

The 7600’s “deeply pipelined” reputation in the textbook tradition is anchored in this set of timings. Six of the nine units are pipelined into 2-5 stages each; the divide unit is not pipelined but can start a new operation 18 cycles after a previous one (per Edinburgh’s reference). This is what subsequent textbooks call “the canonical first deeply pipelined scalar scientific computer.” The 6600 had parallel functional units that each completed before accepting the next instruction; the 7600 broke those units into stages and overlapped successive instructions through them.

The control logic that orchestrated dispatch is the CIW register:

“The control logic associated with the CIW register … serves the same purpose as the Scoreboard in the 6600, but is somewhat less complex.”18

This is sometimes characterized as a “simplified scoreboard”: instructions issue in order (one per minor cycle), with the dependency-tracking that the 6600’s scoreboard did dynamically being handled at issue time. In return for the simplification, the 7600 got the deeper pipelines and the higher clock rate.

Instruction stack – 12 deep

The 7600 included an instruction word stack of twelve 60-bit registers that functioned as a small instruction prefetch/loop buffer:

“The instruction word stack is a group of twelve 60 bit registers in the CPU computation section which hold program instruction words for execution. The instruction stack information is essentially a moving window in the program code. The stack is filled two words ahead of the program address currently being executed. A small program loop may frequently be entirely contained within the instruction stack. When this happens the loop may be executed repeatedly without further references to SCM.”19

The 12-deep stack thus served two functions: (1) instruction prefetch, hiding SCM access latency, and (2) a loop cache, keeping tight inner loops resident in the CPU and freeing SCM bandwidth for data. Some secondary sources (HandWiki) call this “instruction pipeline” – a slight misnomer, since pipelining proper happens in the functional units; the 12-stack is more properly an instruction-buffer/loop-cache. A loop of up to ~40 instructions (10 60-bit words at four instructions per word) could be fully resident.

This was a precursor to dedicated loop buffers (Pentium 4) and micro-op caches (Sandy Bridge onward).

Peripheral Processing Units (PPUs) – 15 (not 10)

The 7600 had 15 PPUs, an increase from the 6600’s 10. The brochure specifies:

“A maximum of 15 PPU may be directly connected to the CPU. … All 15 CPU input-output channels may be in operation at the same time.”20

Each PPU was a 12-bit computer with 4096 12-bit words of core memory at 275 ns cycle time, on a 27.5 ns clock. As on the 6600 there was a barrel-processor implementation (one physical PPU datapath time-multiplexed across the multiple register banks), but at the higher 7600 clock and with more PPUs.

The PPU role was the same as on the 6600: handle all I/O, OS scheduling, and operator-console interaction. The CPU never executed an interrupt handler.

A subtlety: the brochure makes a distinction between “directly connected” PPUs at the CPU end (these are the canonical 15 channels, each with assembly/disassembly registers between 12-bit PPU and 60-bit CPU) and the “system” or “peripheral equipment controller” PPUs which sat further out toward the I/O equipment. The “15 PPUs” usually quoted in secondary sources is the 15 directly-connected CPU channels – the count of 60-bit-to-12-bit assembly/disassembly registers in the I/O section. The actual count of peripheral processors that an installation might have varied with configuration. The HandWiki-cited “10 PPUs based on CDC 160-A” appears to refer to a typical minimum CDC-recommended configuration (one Maintenance Control Unit, four system PPUs, plus a few PPUs at operating stations) rather than the maximum of 15.

Confidence: HIGH that 15 channels is the architectural max; MEDIUM on the typical-installation count.

Memory hierarchy – the architectural innovation

The 7600’s two-level memory hierarchy is the design choice that subsequent textbooks single out. The CDC Preliminary System Description sets the architectural scene:

“The CPU contains two types of internal core memory. One type, designated as the small core memory (SCM), is a many bank coincident current type memory with a total capacity of 64K words of 60 bit length (K = 1024). The other type, designated as the large core memory (LCM) is a linear selection type of memory in which eight 60 bit words are addressed as a single unit. The LCM has a total capacity of 500K words of 60 bit length.”21

Small Core Memory (SCM)

  • Capacity: 65 536 60-bit words (the brochure says “64K words”; the LLNL placard says 65 000; the 65 536 figure is the precise binary value).
  • Cycle time: 275 ns full read/write cycle = 10 minor cycles. The brochure: “Each SCM bank has a four clock period access time from arrival of the storage address to readout of the 60 bit word. The total read/write cycle time for a SCM bank is ten clock periods.”22 So access (latency) is 110 ns; full cycle is 275 ns.
  • Banks: 32 independent banks of 2K words each. “It is thus possible for a maximum of ten SCM banks to be in operation at one time.”
  • Function: SCM is the working memory for the currently-executing program. CPU instructions and CPU operand data both reside here. The first 4K addresses are I/O buffers; the next 1K is the resident OS monitor; the rest is for the active object program.

Large Core Memory (LCM)

  • Capacity: 512 000 60-bit words (some sources round to 500K; canonical figure is 500K-512K range, with 512 000 as the standard quoted value).
  • Cycle time: 1760 ns = 1.76 microseconds = 64 minor cycles. The brochure: “A storage reference to a LCM bank results in a read/write cycle which takes 64 clock periods.”23 (Note: 64 x 27.5 ns = 1760 ns exactly. Some sources round to 1.7, others to 1.8; 1.76 microseconds is the precise figure.)
  • Banks: 8 independent banks of 64K words each. “Eight 60 bit words are read simultaneously from a LCM bank whenever a read/write cycle occurs. These words are held in a 480 bit operand register for each LCM bank.”24
  • Word width: 480 bits (eight 60-bit words read in parallel) plus 4 parity bits per 60-bit word, giving 512 bits of raw memory per LCM word position.
  • Function: bulk staging memory. Object programs are assembled in LCM. Data files are buffered through LCM. Large arrays that don’t fit in SCM are addressed directly in LCM during execution.

The two-level model

The 7600 was the first commercial scientific computer to expose a software-managed memory hierarchy of this style. The architectural picture:

  • CPU runs out of SCM only for code (program runs out of SCM). Active inner loops fit in the 12-deep instruction stack and need no SCM at all.
  • Active small data fits in SCM.
  • Bulk data sits in LCM, with software-driven block-copy instructions between SCM and LCM (the CDC 7600 instruction set has explicit BLOCK COPY operations between SCM and LCM).
  • Disk and tape are connected through PPUs with longer-still latencies.

This is conceptually a three-level hierarchy (registers / SCM / LCM / disk), and the CPU’s “fast” memory is SCM with LCM as a bulk overflow.

“If the program and associated data are too large to fit entirely in SCM a portion of the data must be retained in LCM and directly addressed there. This must be done by declaration at compile time in order to designate certain arrays of data to reside in LCM for execution.”25

This is software-managed staging. The programmer (or the FORTRAN compiler with declaration directives) decides what lives in SCM and what stays in LCM. There is no hardware cache. The CPU has direct addressing of both SCM and LCM, with the latency difference being entirely visible to the program.

This is what subsequent computer architecture textbooks call the precursor to caches – a two-tier main memory with a fast level (SCM) and a slow but larger level (LCM), conceptually like the L1 cache + main RAM split that became standard in the late 1980s. The crucial difference: the 7600 leaves staging entirely to software; modern caches are hardware-managed.

It is also the major source of programmer complaint in 7600 software development. Every nontrivial 7600 program had to think hard about what data went where and when to block-copy between SCM and LCM. LLNL’s LTSS, NCAR’s custom OS, and CERN’s job-control workflow all evolved elaborate machinery to manage this. The Cray-1, designed three years later (delivered 1976), would explicitly reject the SCM/LCM model in favour of a single fast memory plus vector registers as the implicit “cache” – and Cray’s choice was deliberately driven by feedback from 7600 customers who had spent years fighting the staging problem.

Comparison to caches

The 7600’s SCM/LCM hierarchy is conceptually the same shape as a modern L1/L2 cache hierarchy: a small fast level explicitly addressable, a large slow level accessible at higher latency. The fundamental architectural choice – two levels with different access times under one address space is the precursor to all subsequent cache hierarchies (IBM 360/85 in 1968 introduced the first hardware cache; the 7600 of 1969 introduced the explicit-software equivalent at supercomputer scale).

In the 7600 the programmer manages the hierarchy explicitly; in modern caches the hardware does it transparently. The conceptual lineage is direct.

Confidence: HIGH on all numbers (the 1968 Preliminary System Description is the primary source, and all secondary sources concur).

Physical / mechanical

Cabinet shape – C, not Y

A common misconception: the 7600 cabinet is C-shaped, not Y-shaped. (The Cray-1 of 1976 was C-shaped too; the Cray-2 of 1985 was the rectangular tower; none of Cray’s CDC- or Cray Research-era machines used a Y-shaped chassis.)

“[T]he 7600 was redesigned into a large ‘C’ shape to allow access to the modules on either side of the cooling piping by walking into the inside of the ‘C’ and opening the cabinet.”26

“The physical C-shape both reduced floor space and dramatically increased performance by reducing the distance that signals needed to travel.”

The 6600 had been a “plus sign” / cylindrical-cross with four arms radiating from a central column. The 7600 was a different geometry: a single tall arc, opened from one side, with cordwood modules accessible by walking inside the C. This was a deliberate response to the 6600’s serviceability problem (the 6600’s plus-sign packed modules on the inner surfaces of arms, making them harder to reach without disassembling cooling piping).

Dimensions (per Wikipedia / HandWiki):

  • Height: 188 cm (74 in)
  • Width: 302 cm (119 in) (about 6 feet by 10 feet footprint approximately; the “width” is the chord across the C)
  • Depth/floor space: roughly comparable to a 6600 cabinet – the 7600 was actually slightly more compact than the 6600.

Cooling – freon-water, redesigned by Dean Roush

Dean Roush, the refrigeration engineer who had designed the 6600’s freon system, designed the 7600’s. The basic concept was carried forward; the implementation was refined:

“For the 7600, Cray once again turned to his refrigeration engineer, Dean Roush, formerly of the Amana company. Roush added an aluminum plate to the back of each side of the cordwood stack, which were in turn cooled by a liquid-freon system running through the core of the machine.”27

The 7600’s heat density was higher than the 6600’s (more transistors per unit volume in the eight-board cordwood modules) and the cooling system was correspondingly more aggressive. Liquid freon vapourised at the cordwood-module aluminium plates, condensed in heat exchangers at the central column of the C, and dumped heat to a building-supplied chilled-water loop.

Power consumption: 95 kW at 208 V 400 Hz (per Wikipedia and HandWiki).

Logic family – discrete transistors, not yet ECL ICs

The 7600 used high-speed discrete silicon transistors in cordwood modules. It was not built with emitter-coupled-logic integrated circuits, despite ECL being known and used in some contemporary military computers. The 1969-1970 production timeframe was right at the cusp of the IC transition.

“The CDC 7600 used circuit modules that actually consisted of up to six printed circuit boards, each one stuffed with subminiature resistors, diodes, and transistors. The six boards were stacked up and then interconnected along their edges, making a very compact, but basically unrepairable module.”28

The brochure schematic and the LLNL placard both indicate the 7600’s 3 360 modules per system. The HandWiki article specifies “high-speed discrete transistors in an eight-board circuit module”; secondary sources are consistent on the discrete-transistor / multi-PCB cordwood design. (Note: the 7600 cordwood module had six PCBs per module per the more detailed Wikipedia description, with HandWiki citing eight; this is one of the few architectural details where secondary sources disagree slightly. The most reliable figure is six PCBs per module; the eight-board figure may be a count that includes mounting-frame substrate boards.)

The logic family: the 6600 had used Direct-Coupled Transistor Logic (DCTL); the 7600 used higher-speed discrete-transistor logic that was effectively a specialised current-mode design, but not yet packaged as ECL integrated circuits. The first CDC machines to use ECL ICs were the Cyber 170-1xx series (~1973) and later. The 7600’s “ECL” is sometimes misattributed because the same Cyber product family eventually moved to ECL, but the 1969-1970 7600 was discrete-transistor.

Transistor count

Estimating: 3 360 modules x ~6 PCBs/module x ~50-100 transistors/PCB suggests ~1-2 million transistors per system. This is several times the 6600’s 400 000. Specific published figures are not readily available in the open literature; this is a known gap in the secondary-source record.

Confidence: LOW on transistor count. HIGH on cordwood / discrete-transistor / six-PCB module design. HIGH on the non-ECL point.

Wiring

Per the LLNL placard: 120 miles of wire per system. The 6600 had had ~100 miles of wire; the 7600 increased that with the higher transistor count and the more elaborate cooling.

Cost

The placard says $5.1 million for serial #1 (LLNL, January 1969). Wikipedia gives “around $5 million in base configurations” and a monthly rental range of $62 000-$155 000 in 1968 dollars. The secondary literature converges on $5 million for a base 7600 system, up to $15 million for top-end installations with full LCM, multiple PPUs, and disk arrays.

Confidence: HIGH on the $5 million baseline; MEDIUM on the $15 million top-end figure (it appears in Murray and in HPC retrospectives but no single primary-source price list).

The 6800 to 7600 rename, in detail

The internal CDC 6800 designation was used through 1965-1966 in design documents at Chippewa Falls. By 1967, as the design matured, Cray made two decisions that broke 6600 compatibility:

  1. The I/O architecture was completely redesigned – the 7600 has 15 directly-connected channels with assembly/disassembly registers and a different PPU communication protocol, where the 6600 had its 12 channels via a different scheme. Operating-system code that talked to channels would not run.
  2. The SCM/LCM model required new instructions – block-copy operations between the two memories, and the LCM had different addressing.
  3. Some control instructions were repurposed – the simplified-scoreboard CIW register replaced the 6600’s full Scoreboard, with consequences for how certain “wait-on-result” instructions behaved.

Cray’s choice was: keep 6600-level user-code compatibility (FORTRAN programs would generally work, with some recompilation), but break system-code compatibility. The decision was that this break was severe enough that customers could not legitimately expect their full 6600 software stack to run, and so a new model number was needed.

The CDC marketing decision – 7600 rather than 6800 – followed CDC’s general numbering convention. The 6000 series (6400, 6500, 6600, 6700) was the existing CDC line. The “7000” prefix marked a new series; the “600” suffix was retained as a quasi-tradition tying the new flagship to its predecessor. Within the CDC sales taxonomy, “7600” said both “compatible with 6600 user code” and “not the same product family as 6600.”

This pattern would repeat at CDC: the 8600 was Cray’s never-finished further evolution, and the STAR-100 was a separate vector machine. But the 7000-numbering scheme was effectively a one-machine product line; only the 7600 (and its Cyber 76 / Cyber 175 cousins) ever shipped under it.

Architectural lineage forward

Deep pipelining → vector pipelines (Cray-1, 1976)

The 7600’s pipelined floating-point units were the bridge between the 6600’s parallel-but-not-pipelined functional units and the Cray-1’s vector pipelines. The 7600’s add-pipeline, for instance, accepted one operand pair per minor cycle and produced one result per minor cycle after a 4-cycle latency – which is exactly the model the Cray-1’s vector add unit operated on, except the Cray-1 chained successive operands together as a vector and the result of the add pipe could be chained directly into a multiply pipe to produce a fused-multiply-add throughput.

The Cray-1 added vector registers (eight 64-element registers) to abstract over the pipelined units; the Cray-1’s scalar functional units were direct descendants of the 7600’s pipelined functional units. In Cray’s own design philosophy: the Cray-1 was the 7600 with vector machinery layered on top.

SCM/LCM → cache hierarchy (1980s onward)

The 7600’s two-level memory hierarchy is the conceptual ancestor of the modern cache hierarchy. The IBM 360/85 of 1968 introduced the first transparent hardware cache (16-32 KB on a 360 main memory); the 7600 of 1969 introduced the explicit two-level memory at supercomputer scale. By the early 1980s, microprocessor designs (Motorola 68020, Intel 80386) had on-chip caches; by the 1990s, multi-level caches (L1, L2, eventually L3) were universal.

The 7600’s lesson was twofold: (1) two-level memory hierarchies are necessary to feed fast pipelines, and (2) software-managed hierarchies are painful. The path forward was hardware-managed caches.

Cray-1: the explicit move away from explicit memory hierarchy

When Cray designed the Cray-1 between 1972 and 1976, he made a deliberate architectural decision to abandon the SCM/LCM model. The Cray-1 had a single fast main memory (16 banks of 64K words, ~50 ns access time) and no slower bulk memory at the CPU level. The argument was: customers had spent five years fighting the 7600’s SCM/LCM staging problem, and the resulting code complexity wasn’t worth the bytes saved.

The Cray-1 substituted the vector registers (eight 64-element 64-bit vector registers, ~512 bytes total) as a kind of fast intermediate level – not a cache but a programmer-visible register file, used to amortise memory latency over chunks of data. This made the Cray-1’s memory model conceptually simpler than the 7600’s: there was just one memory, plus the vector and scalar registers.

In retrospect, Cray’s choice was both correct (for the 1976 Cray-1, with its 1 megabyte of fast memory) and incorrect (as memories grew and the gap between processor speed and memory speed widened, two-level hierarchies became unavoidable; the Cray X-MP and Y-MP brought back caches, and the Cray-2 of 1985 had its own SCM-like “local memory” per processor). The Cray-1’s clean single-memory model was a reaction to the 7600’s painful two-level model, and the post-1985 Cray family eventually reintroduced hierarchy in different form.

Architectural lineage sideways

Comparison to IBM 360/91

Both the 7600 (delivered 1969) and the IBM 360/91 (delivered 1967) are single-issue out-of-order scientific machines from the same architectural era, designed by competing teams trying to solve the same problem. The contrast is illuminating.

Feature CDC 7600 (1969) IBM 360/91 (1967)
Word 60-bit 32-bit / 64-bit (System/360 architecture)
Clock 27.5 ns 60 ns
Issue width 1 instruction/cycle 1 instruction/cycle
Reordering Simplified scoreboard at issue Tomasulo’s algorithm with reservation stations + CDB
Renaming None Yes (via reservation-station tags)
Pipeline depth 2-5 stages per FU 6 cycles per multiply, 18 per divide, less pipelined
Functional units 9 deeply pipelined Adder + multiplier-divider, fewer units
Memory hierarchy SCM (275 ns) + LCM (1760 ns) Sixteen-way interleaved core (780 ns)
Floating-point 60-bit fixed format IEEE-precursor 32 / 64 bit
Imprecise interrupts No (in-order issue) Yes (out-of-order completion)
Units shipped ~75 14-15
Performance peak 36 MFLOPS ~16 MFLOPS
Performance sustained 10-15 MFLOPS ~4-6 MFLOPS
Cost $5-15 M $7-15 M
Customer base Research / weapons / academic Few research / aerospace

Architectural verdict:

  • The 7600 has deeper pipelines but simpler scheduling – it issues in order with a reduced scoreboard (vs the 6600’s full scoreboard). It compensates for the simpler scheduling with the deeper pipes and the higher clock rate.
  • The 360/91 has more aggressive scheduling (Tomasulo’s reservation stations with register renaming, Common Data Bus broadcast) but shallower pipelines. The 91’s microarchitecture was the first commercial out-of-order with renaming, and its imprecise-interrupt cost is what kept the algorithm from migrating to mainstream IBM 360s.
  • The 7600 won commercially: ~75 units vs the 91’s 14-15, and the 7600 was the canonical scientific supercomputer of the early 1970s while the 91 was an isolated curiosity.
  • The 91’s algorithm won architecturally: Tomasulo’s algorithm in the 360/91 is the direct ancestor of every modern out-of-order CPU (Pentium Pro 1995 and after); the 7600’s simplified scoreboard is not in the lineage.

The two machines are perfectly contrasted. Cray bet on higher clock + deeper pipes + simpler scheduling; IBM bet on lower clock + shallower pipes + more aggressive scheduling. Cray’s bet won the commercial supercomputer market; IBM’s bet won the long architectural war for general-purpose CPUs three decades later.

Comparison to the 6600

Feature CDC 6600 (1964) CDC 7600 (1969)
Clock 100 ns 27.5 ns (3.6x faster)
Functional units 10 parallel, not pipelined 9 mostly pipelined
Issue mechanism Full Scoreboard, out-of-order CIW with simplified scoreboard, in-order
Memory 32K-128K words at 1 us 64K SCM (275 ns) + 512K LCM (1760 ns)
Cabinet Plus-sign / four-arm C-shape
Cooling Freon, full Freon, refined by Roush
Logic Silicon DCTL, ~6000 modules Silicon discrete-transistor, ~3360 modules (denser)
Wiring ~100 mi ~120 mi
Peak ~3 MFLOPS ~36 MFLOPS
Sustained ~0.5-1 MFLOPS ~10-15 MFLOPS
Speedup – ~10x over 6600
Units shipped ~100 ~75
First ship September 1964, LLNL January 1969, LLNL
Cost $7-10 M $5-15 M

The interesting cross-comparison is that the 7600 had fewer functional units (9 vs 10) and simpler issue logic (in-order with reduced scoreboard vs full out-of-order scoreboard) but ran 10x faster overall. The performance gain came almost entirely from (a) the 3.6x clock, and (b) the pipelining that turned 4-cycle adds into 1-cycle-throughput adds.

Cray’s architectural insight at the 6600-to-7600 transition was that deeper pipes plus a faster clock beat parallel non-pipelined functional units. This was the lesson that vectored straight into the Cray-1 (which simplified further by putting everything onto a single fast memory and adding vector registers).

Customers (partial list)

The 7600 customer base was the same set of scientific institutions that had bought the 6600 a few years earlier, often as 7600-replacing-6600 upgrades. Confirmed customer sites:

  • Lawrence Livermore National Laboratory (S/N 1, January 1969 - October 1988): nuclear weapons design, plasma simulation. Ran the Livermore Time Sharing System (LTSS); pioneered the Octopus network connecting hundreds of remote terminals. Retired when LLNL accepted the world’s first Cray-2 in 1985, although the actual physical retirement of the chassis was October 1988.
  • National Center for Atmospheric Research, Boulder (S/N 12, May 1971 - Spring 1983): atmospheric general circulation modelling. Decommissioned in 1983 in favour of a second Cray-1A (S/N 14). Ran NCAROS, NCAR’s custom OS. NCAR developed its own FORTRAN 70 compiler. ~12 years of service.
  • CERN, Geneva (installed March 15 1972 - disconnected 1984): particle physics simulation. Replaced CERN’s CDC 6600 (which had been there since 14 January 1965). The CDC 7600 module currently on display at CERN was installed in 1972; “the CDC 7600 was finally disconnected in 1984.”
  • Lawrence Berkeley National Laboratory: high-energy physics analysis.
  • Los Alamos National Laboratory: nuclear weapons design.
  • University of Manchester (UK, ca. 1972 – per a 1974 photograph at chezfred.org.uk): academic computing.
  • University of London: a 7600 circuit card from London University Computing Centre is referenced in CHM materials. Likely 1972-onward installation.
  • Cambridge University: not specifically confirmed; some secondary sources mention.
  • NASA centres: NASA Ames Research Center had a 7600 by the early 1970s.
  • U.S. National Security Agency: NSA bought multiple CDC supercomputers; a 7600 procurement is likely though specific details remain classified.

The total customer mix was approximately the same as the 6600’s: heavy weighting toward U.S. weapons laboratories, particle-physics centres, NASA, and major research universities, with European centres (CERN, Manchester, London, possibly others) representing the international fraction.

Confidence: HIGH on LLNL, NCAR, CERN. MEDIUM on Manchester. LOW on a comprehensive list (no single open-record source enumerates all 75 deliveries).

NWP and atmospheric science use

The 7600 was the NCAR primary supercomputer from May 1971 to spring 1983 – a full twelve years. During this period:

  • The Kasahara-Washington NCAR GCM (which had been initially developed on the NCAR CDC 6600 in 1965-1971) was ported to the 7600. The 7600 ran higher-resolution and longer-integration GCM simulations than the 6600 had been able to.
  • Warren Washington’s more elaborate NCAR Community Climate Model work of the 1970s ran on the 7600.
  • Akira Kasahara’s continued atmospheric-dynamics research was on the 7600.
  • The 7600 served as the computational core for NCAR’s transition from a 1960s-era research GCM facility to a 1970s-1980s climate-modelling powerhouse.

The 7600’s reliability problems mattered here: NCAR’s CISL records that the centre had to invest heavily in checkpoint/restart machinery to compensate for the multiple-failures-per-day reliability characteristic of the 7600. NCAROS was custom-developed for the 7600 in part to provide automated job recovery.

The 7600 was not in operational weather forecasting use. The U.S. National Meteorological Center at Suitland was, in this period, on IBM 360/195s (1974-1981); the European Centre for Medium-Range Weather Forecasts (founded 1975, operational 1979) ran on its own Cray-1. The 7600 was a research-supercomputer, like the 6600 it had replaced.

The 7600 in retrospect

The 7600 is the bridge machine. It sits architecturally between the 6600’s parallel-functional-units design and the Cray-1’s vector-pipeline design. It introduced the two-level main-memory hierarchy that later became standard (in the form of caches). It established deep pipelining as the canonical scientific-computer design technique. It made Seymour Cray famous for the second time, after the 6600 had made him famous for the first.

Its commercial success (~75 units, world’s fastest 1969-1975) is moderate by the standards of the 6600 (~100 units, world’s fastest 1964-1969) but extraordinary by the standards of contemporary IBM machines (the 360/91 sold 14, the 360/195 sold ~20). The 7600 was profitable for CDC, kept Chippewa Falls funded, and bridged Cray’s career from the architectural triumph of the 6600 to the personal triumph of leaving CDC in 1972 to found Cray Research.

The 7600’s reliability problems and the SCM/LCM staging burden are the negative architectural legacy. They are the architectural decisions Cray most consciously rejected when designing the Cray-1.

The 7600’s positive architectural legacy – deep pipelining, two-level memory hierarchy, simplified instruction issue at higher clock – is in every modern microprocessor.

Anecdotes

The 7600 as the “6600 done right”

Jim Smith (the architect of the Astronautics ZS-1 and one of the most consequential 1980s computer architects) characterised the 7600 in 2001:

“The pipelined, in-order issue 7600 is the 6600 ‘done right.’”29

The 7600 simplified and rationalised the design choices of the 6600. The 6600’s full-scoreboard out-of-order issue was elegant but only modestly performance-relevant given the 6600’s parallel-non-pipelined functional units; the 7600 traded that for pipelined functional units and a simpler issue mechanism, and got more performance.

Cray’s design tools, again

Cray designed the 7600 the same way he designed the 6600: with #3 Ticonderoga pencils on graph paper, no CAD, working alone or in close consultation with Thornton. The Chippewa Falls laboratory continued to operate at roughly thirty to thirty-five engineers and a janitor through the 7600 design period.

The grounding-loop problem

The 7600’s higher clock rate exposed a real engineering problem at CERN: ground-loop currents on the inter-module wiring caused intermittent faults. The CERN 7600 had to have all modules fitted with sheathed rubber bands to break the ground loops. This is a small but vivid detail of what “supercomputing” actually meant in 1972.

The Cyber 76

In 1971 CDC marketing rebranded a 7600-derivative as the CDC Cyber 76. The Cyber 76 was effectively a 7600 with cosmetic packaging differences and slightly different I/O. It was sold into customer accounts that wanted “Cyber” branded equipment. The Cyber 76 – and its 1973 successors the Cyber 175 and 176 – carried the 7600 architectural lineage forward into the late 1970s.

Cray’s conditional reaction to “deep pipelining”

The 7600’s pipelining was, in Cray’s own design notes, a reaction to the realisation that the 6600’s “ten parallel functional units” could not be made faster individually – the 100 ns clock was already at the edge of the silicon transistors’ switching time. The only way to get more throughput was to stage the units’ work and pipeline. This is a recurring theme in Cray’s design philosophy: when raw clock speed runs out, find a way to extract more parallelism from each cycle. Pipelining was the 7600’s answer; vectorisation was the Cray-1’s; symmetric multiprocessing was the X-MP / Y-MP’s. Cray came back to the same insight three times across his career.

Sources

Primary

CDC Preliminary System Description, November 1968. “Control Data 7600 Computer System: Preliminary System Description, November 1968. Copyright 1968 Control Data Corporation, Printed in the United States of America.” Computer History Museum brochure collection, catalog ID 102646087, available as PDF at http://s3data.computerhistory.org/brochures/cdc.7600.1968.102646087.pdf. THE primary technical reference for the 7600 architecture as designed and announced. All architectural figures (clock, memory cycle times, banks, functional unit counts, instruction-stack size, PPU count) cited above are from this document. Pages 1-26 of the brochure contain the system description, with detailed tables for SCM, LCM, PPU, and I/O channel specifications.

CDC 7600 Preliminary Reference Manual, 1969. Control Data Corporation. Internet Archive, https://archive.org/details/cdc7600hwrm. 616 pages. The detailed hardware reference manual for the 7600, with full instruction set and timing details. Uploaded by harryhaller02 in February 2017.

LLNL Serial #1 placard. Computer History Museum catalog X1385.97U, “CDC 7600 Supercomputer Section.” The placard affixed to the surviving CPU section reads verbatim: “CDC 7600 S/N 1 – Delivered 01/69 retired 10/88 Cost: $5.1 million – 36 million operations per second – 4,000,000 bytes (chars) magnetic core memory – Small core memory: 65,000 60-bit words – Large core memory: 512,000 60-bit words – 3,360 modules – 120 miles of wire.”

Secondary – canonical popular history

Murray, Charles J. The Supermen: The Story of Seymour Cray and the Technical Wizards Behind the Supercomputer. New York: John Wiley & Sons, 1997. ISBN 978-0471048855. The canonical popular history of CDC and Cray; covers the 6600 to 7600 transition, the Chippewa Falls laboratory through the late 1960s, and the 7600’s reliability issues.

Bell, C. Gordon, J. Craig Mudge, and John E. McNamara. Computer Engineering: A DEC View of Hardware Systems Design. Bedford, MA: Digital Press, 1978. A standard reference for early-1970s computer architecture. Contains comparison material on contemporary scientific computers including the CDC 7600. Internet Archive: https://archive.org/details/ComputerEngineeringADecViewOfHardwareSystemsDesign.

Computer History Museum

  • “December 3: CDC Announces 7600 Supercomputer.” CHM This Day in History. https://www.computerhistory.org/tdih/december/3/. Canonical primary-secondary source for the announcement date.
  • “CDC 7600 supercomputer section – X1385.97U.” CHM Catalog (Lawrence Livermore serial #1). https://www.computerhistory.org/collections/catalog/X1385.97U. Authoritative source for the LLNL placard.
  • “CDC 7600 at Lawrence Livermore Laboratory – 102634538.” CHM Catalog. https://www.computerhistory.org/collections/catalog/102634538.
  • “7600 LBA module – 102696521.” CHM Catalog (preserved memory address-buffer module).
  • “7600 SG module – 102696554.” CHM Catalog (preserved 7600 hardware module).
  • “ECL (Emitter Coupled Logic), CDC, circa 1975 – 102681042.” CHM Catalog. (Note: this 1975 ECL CDC module is from the Cyber 170 era, NOT the 7600 of 1969.)

NCAR / atmospheric science

CERN

LLNL

  • Lawrence Livermore National Laboratory, Sixty Years of Innovation, 1969 chapter. https://www.llnl.gov/sites/www/files/1969.pdf. Contains the LLNL retrospective on the 7600 era including the Cray-CDC relationship, LTSS development, and the eventual 1985 transition to Cray-2.
  • LLNL Flickr photograph “CDC 7600 Computer.” https://www.flickr.com/photos/llnl/3094206572. December 2008 upload of the in-production 7600 with caption.
  • Fong, K. W., “LTSS compendium: an introduction to the CDC 7600 and the Livermore Timesharing System.” LLNL UCID-17556, 1977. https://www.osti.gov/biblio/5233541/. Companion: “CDC 7600 LTSS Programming Stratagems” (UCID-17557).

Architectural detail

Computing History (UK)

Cray and Cray Research

IBM 360/91 cross-reference (for the architectural comparison)

  • “IBM System/360 Model 91.” Wikipedia. https://en.wikipedia.org/wiki/IBM_System/360_Model_91. The contemporary IBM machine for cross-comparison.
  • Tomasulo, R. M., “An Efficient Algorithm for Exploiting Multiple Arithmetic Units,” IBM Journal of Research and Development 11(1):25-33, January 1967. DOI 10.1147/rd.111.0025. The canonical Tomasulo paper, for architectural comparison with the 7600’s simpler scoreboard.

Cross-references in our existing research

  • /research/computers/CDC_6600.md – detailed companion file on the 6600 (predecessor architecture).
  • /research/computers/IBM_360_91.md – companion file on the 360/91 (architectural contemporary).
  • /research/computers/IBM_360_91_business.md and /research/computers/IBM_360_91_customers.md – customer-list and antitrust context for the 360/91.
  • /research/computers/Cray-1.md – companion file on the Cray-1 (architectural successor / repudiator of the 7600’s SCM/LCM model).
  • /research/computers/CDC_1604.md – earlier Cray machine.
  • /research/computers/CDC_founding.md – CDC corporate history context.

Confidence flags

HIGH confidence (multiple primary or near-primary sources agree):

  • 60-bit word, retained from 6600
  • 27.5 ns clock cycle (36.4 MHz), 275 ns major cycle
  • 9 functional units in the central processor
  • Pipeline stages per unit (2 for Boolean/Add/Shift/Increment, 4 for Floating Add, 5 for Floating Multiply two-pass, 20 unpipelined for Divide, 3 for Normalize, 2 for Population Count)
  • 12-deep instruction word stack functioning as both prefetch and small loop cache
  • 65 536 word SCM at 275 ns full cycle (110 ns access), 32 banks
  • 512 000 word LCM at 1760 ns full cycle, 8 banks (1.76 microsecond)
  • 15 directly-connected PPU channels at the CPU end
  • C-shaped chassis with internal access from the open side
  • Liquid freon cooling redesigned by Dean Roush
  • Discrete silicon-transistor cordwood modules (NOT ECL ICs); approximately 3 360 modules per system
  • 120 miles of wire per system
  • 188 cm (74 in) tall, 302 cm (119 in) wide
  • 95 kW at 208 V 400 Hz
  • Public announcement 3 December 1968
  • First customer ship: January 1969 to LLNL as serial #1
  • LLNL serial #1 cost $5.1 million; retired October 1988
  • ~75 units shipped worldwide
  • World’s fastest computer 1969-1975
  • 6800 → 7600 rename: instruction-set incompatibility with 6600
  • Originally CDC 6800; renamed during 1967 design phase
  • Pipelining-not-parallelism is the central architectural shift from 6600 to 7600
  • SCM/LCM is software-managed, not hardware-cache
  • NCAR serial #12, May 1971; CERN delivered March 1972; both retired the 7600 in early 1980s

MEDIUM confidence (strong secondary sourcing but I’d want to double-check primary sources):

  • The exact month/year of the 6800 → 7600 rename within 1967 (multiple sources say “during the design” but no precise date)
  • “Approximately 75 units” – the most reliable single number, but some sources give 40 or 50; the 1978 Science magazine reference behind the 75 figure has not been verified
  • Cordwood module composition: 6 PCBs vs 8 PCBs (sources disagree slightly; 6 is the more common figure)
  • Top-end configuration cost $15 million (Murray-cited; primary-source price-list documentation not available)
  • Instruction count “~72-74 opcodes” – broadly cited but no precise figure
  • Performance “5x to 10x over 6600” – the workload-dependent range is well attested; “10x” is the canonical figure but “5x” is also common
  • Dean Roush biographical claim that he was formerly of Amana
  • The specific list of all 75 customer sites (only ~10 are confirmed in open-record secondary sources)

LOW confidence (treat as anecdote or open question):

  • Total transistor count per system (estimated 1-2 million, but no published figure found)
  • Total weight of the 7600 chassis
  • Precise floor-space requirement (general “smaller than 6600” is well-attested; precise square footage is not)
  • The “Cyber 76” production count distinct from 7600
  • Whether NSA bought a 7600 (likely but not confirmed in open record)
  • Whether U.S. Air Force, Naval Postgraduate School, or Sandia had 7600s (probable but not confirmed)
  • The exact number of “directly-connected PPUs” in a typical installation (architecture max is 15; practical installations varied)

Note on the post arc

The 7600 sits at a critical transition in the NWP / HPC story:

  • It is the first deeply pipelined commercial scientific computer, the design that established pipelining as the canonical way to extract performance from a fast scientific CPU.
  • It is the first commercial machine with a two-level main-memory hierarchy, and so the precursor to the modern cache hierarchy.
  • It is the last great machine Cray built at CDC, before he left in March 1972 to found Cray Research.
  • It is the bridge between the parallel-functional-units 6600 and the vector Cray-1.
  • It is the canonical “deeply pipelined” machine that David Patterson and John Hennessy hold up as the early-1970s archetype in their Computer Architecture textbook.
  • It is the machine NCAR ran for twelve years (1971-1983), doing the Kasahara-Washington GCM, the early Warren Washington community-climate-model work, and the full transition to second-generation atmospheric simulation.
  • It is the architectural sibling of the IBM 360/91 – both single-issue, both ambitious – and the comparison illuminates what scoreboard vs Tomasulo, deep pipelines vs aggressive scheduling, and 75-units vs 14-units actually meant.

The post can build through architecture (pipelining, SCM/LCM), people (Cray, Roush, Thornton continuing, the Chippewa Falls team), money (~75 sold at $5-15M each), and consequences (the Cray-1’s deliberate rejection of SCM/LCM; the universal cache hierarchy of the 1980s onward). The Watson memo of 1963 sits behind the whole thing as the IBM-vs-CDC backstory; the 7600 is the machine that proved that backstory was right – IBM never caught up commercially, and the 7600 was world’s fastest from 1969 to 1975, a six-year reign that ended only when Cray himself shipped the Cray-1.

Footnotes

  1. Control Data Corporation, 7600 Computer System: Preliminary System Description, November 1968, p. 1 (Introduction). Computer History Museum brochure 102646087. ↩

  2. Ed Thelen comp-hist, “Control Data Corporation, CDC-6600 & 7600,” https://ed-thelen.org/comp-hist/vs-cdc-6600.html. ↩

  3. HandWiki, “CDC 7600,” https://handwiki.org/wiki/CDC_7600. ↩

  4. Computer History Museum, “December 3: CDC Announces 7600 Supercomputer,” This Day in History, https://www.computerhistory.org/tdih/december/3/. ↩

  5. Computing History UK, “CDC announces the 7600 supercomputer,” https://www.computinghistory.org.uk/det/6125/CDC-Introduces-the-7600-Supercomputer/. ↩

  6. LLNL Serial #1 placard, Computer History Museum catalog X1385.97U, “CDC 7600 Supercomputer Section.” https://www.computerhistory.org/collections/catalog/X1385.97U. ↩

  7. Lawrence Livermore National Laboratory, Sixty Years of Innovation: 1969 First CDC 7600 Time Sharing and Two-Dimensional Modeling, retrieved from https://www.llnl.gov/sites/www/files/1969.pdf, pp. 40-41. ↩

  8. CDC Preliminary System Description (1968), p. 1 (system parameters block): “synchronous internal logic with 27.5 nanosecond clock period.” ↩

  9. Ibid., p. 1. ↩

  10. Wikipedia, “CDC 7600,” https://en.wikipedia.org/wiki/CDC_7600: “about 10 MFLOPS on hand-compiled code, with a peak of 36 MFLOPS.” ↩

  11. CDC Preliminary System Description (1968), p. 1: “Central processor computation exceeds four times as fast as corresponding computation in the 6600 system.” ↩

  12. NCAR/CISL, “CDC 7600,” https://www.cisl.ucar.edu/ncar-supercomputing-history/cdc7600. ↩

  13. CERN Document Server record 2272997, https://cds.cern.ch/record/2272997. ↩

  14. CDC Preliminary System Description (1968), CPU computation section parameters. ↩

  15. Smotherman archive notes; HandWiki: “the 7600 could issue one instruction per cycle regardless of instruction length.” ↩

  16. University of Edinburgh, “Functional units in the CDC 7600,” https://homepages.inf.ed.ac.uk/rni/comp-arch/Paru/7600-units.html: “[Branch is] handled via control logic associated with the CIW register rather than in a separate Branch unit.” ↩

  17. Ibid. ↩

  18. University of Edinburgh, “The CDC 7600 central processor,” https://homepages.inf.ed.ac.uk/rni/comp-arch/Paru/7600-cpu.html. ↩

  19. CDC Preliminary System Description (1968), section on “Instruction word stack.” ↩

  20. Ibid., I/O section: “A maximum of 15 PPU may be directly connected to the CPU.” ↩

  21. Ibid., section on “CPU core memory.” ↩

  22. Ibid., section on SCM banks. ↩

  23. Ibid., section on LCM banks. ↩

  24. Ibid. ↩

  25. Ibid., on object-program execution. ↩

  26. Wikipedia, “CDC 7600.” ↩

  27. HandWiki / Wikipedia, on Dean Roush and the 7600 cooling system. ↩

  28. HandWiki, “CDC 7600.” ↩

  29. Jim Smith, 2001, quoted in Smotherman, “CDC 7600,” https://people.computing.clemson.edu/~mark/cdc7600.html. ↩