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CDC 6600 – Research File

Summary in one paragraph

The Control Data Corporation 6600 was the world’s first true supercomputer: announced 28 August 1963, first delivery to Lawrence Livermore National Laboratory in September 1964, ten times faster than the IBM 7090 it dethroned and approximately three times faster than the IBM 7030 Stretch. It was a 60-bit machine designed by Seymour Cray and James E. Thornton at a small Chippewa Falls laboratory CDC opened for Cray in 1962. The 6600’s central processor exposed ten parallel functional units overseen by a hardware “scoreboard” – the first commercial implementation of dynamic out-of-order issue. Ten Peripheral Processor Units, multiplexed in a barrel architecture, ran the operating system and all I/O so the central CPU could devote itself entirely to numbers. It was packaged in a plus-shaped cabinet with Freon-refrigerant cooling – the first commercial machine where forced-Freon refrigeration was the primary cooling method. About 100 units were sold over the 1964–1972 production run, at roughly $7–10 million each. CERN took serial number 3 on 14 January 1965; NCAR took serial number 7 in December 1965 and ran the first NCAR Global Circulation Model on it from 1965 to 1977. The 6600 launched the lineage CDC 6600 -> 7600 (1969) -> Cray-1 (1976) and is widely cited (Patterson 1985 onward, Hennessy and Patterson 1990 onward) as the architectural ancestor of RISC. It also triggered the most quoted internal memo in computer-industry history: Tom Watson Jr.’s “34 people, including the janitor” memo of 28 August 1963.

Origin (1960–1964)

Cray’s ultimatum and the Chippewa Falls Laboratory

  • By 1962 Cray, having delivered the CDC 1604 (1960) and handed off the CDC 3000-series design, was frustrated with Control Data’s Minneapolis bureaucracy. He confronted CDC president William Norris with what was effectively an ultimatum: build him a remote laboratory or lose him. [The Register, “Remembering the CDC 6600,” 2007; Murray, The Supermen, 1997]
  • Norris agreed. CDC built Cray a laboratory on land Cray owned in his hometown of Chippewa Falls, Wisconsin – about 100 miles east of Minneapolis on the Chippewa River. From this point onwards, every Cray-led machine (6600, 7600, the cancelled 8600, then Cray-1, Cray-2 at Cray Research) was designed at Chippewa Falls, not Minneapolis. [Murray; HandWiki: Seymour Cray; Cray Inc. corporate history]
  • The development team at the lab was small: by the time of the public announcement in August 1963, 34 people – approximately 14 engineers, 4 programmers, plus technicians and support staff. Cray’s principal collaborator was James E. Thornton, who took over most of the detailed circuit-and-functional-unit design while Cray concentrated on system architecture and the critical timing problem. Les Davis was the third senior engineer. [HandWiki: CDC 6600; Murray; The Register, 2007; Wikipedia: Seymour Cray]
  • The 6600 prototype was assembled at Chippewa Falls and demonstrated to CDC management in 1963. The public announcement came 28 August 1963, accompanied by a CDC press release and Business Week coverage. [Wikipedia: CDC 6600; CHM Revolution]
  • First delivery: September 1964, Lawrence Livermore National Laboratory. The CHM holds CPU cabinet 1 of 4 from this Livermore unit (catalog X1385.97F), with $7,000,000 listed as price and 1964 listed as the year of manufacture. Wikipedia’s $2 370 000 figure refers to a per-unit list price for the central-processor cabinet; the full system as delivered to Livermore was $7M and configurations went to roughly $10M for top-end installations. [CHM Catalog X1385.97F; Wikipedia (price discrepancy noted under Cost section)]

Why was it possible? – The technical inflection

  • Silicon transistors had become reliable enough: the 1604 was germanium-transistor; the 6600 was the first CDC machine to use silicon transistors at scale. The CHM Computer History Wiki notes this was a deliberate Cray bet; silicon transistors had crossed germanium switching speed in 1961 and Cray pushed hard to use them despite higher initial unit cost.
  • Cordwood module construction had matured: the 1604’s stackable plug-in module idea was extended to a denser, double-sided “cordwood” form, packaging 64 silicon transistors per module and roughly 6 000 modules per machine. The CHM specifically calls out the 6600 for “first use of Freon cooling and double-sided ‘cordwood’ modules” leading to “greatest component density achieved of its time.”
  • The architectural insight: Cray proposed that one fast central processor could be supplemented by ten small “Peripheral Processors” that handled OS and I/O work. This separation – pure-compute CPU, housekeeping PPs – was the key idea that distinguished the 6600 from contemporaries that mixed I/O and computation in a single CPU.

Architecture: Central Processor and Functional Units

Word, registers, instruction format

  • Word length: 60 bits. [Wikipedia; Thornton, Design of a Computer: The Control Data 6600, 1970; HandWiki]
  • Three classes of registers, eight of each (24 user-visible registers):
    • X0–X7: 60-bit operand / general-purpose data registers
    • A0–A7: 18-bit address registers; loading an address into A1–A5 triggers an automatic memory load into the corresponding X-register, while A6/A7 trigger memory store
    • B0–B7: 18-bit index / scratchpad registers; B0 is hard-wired to zero
  • Instruction format: 15 bits (short) or 30 bits (long, with an 18-bit signed address field). Multiple instructions packed into a 60-bit word; instructions cannot cross word boundaries (no-op padding required for alignment). [Wikipedia; chessprogramming wiki; Museum Waalsdorp]
  • Instruction set size: approximately 74 operation codes (Wikipedia article on RISC and Museum Waalsdorp both cite this number; the Thornton book gives a slightly different breakdown by category). [Wikipedia: RISC; Museum Waalsdorp 6400 hardware article]
  • Two addressing modes only: register+register and register+immediate. This is the architectural detail that Patterson and Hennessy and others later pointed to as the load–store hallmark of RISC. [Wikipedia: RISC]
  • Population count instruction. A specific opcode counts the number of 1-bits in a 60-bit word; the unit was implemented by re-using divide-unit hardware. The instruction was reportedly added at the request of the NSA for cryptanalytic work, and the existence of the instruction in the machine’s specification was, for the cryptanalyst community, a significant signal. [Museum Waalsdorp; multiple secondary sources; Wikipedia: CDC 6600 (footnote on population count)]

The ten parallel functional units

The CPU contained ten functional units, organized into eight functional types with two of the most-used types duplicated for parallelism. The list (from the HASE 6600 simulation, the Edinburgh educational reference, plus the Wikipedia summary) is:

  1. Branch unit – conditional and unconditional jumps
  2. Boolean unit – AND, OR, XOR, complement on 60-bit words
  3. Shift unit – bit shift and rotate
  4. Floating-point Add unit – 60-bit floating-point addition / subtraction
  5. “Long” Add unit – 60-bit fixed-point integer addition (the 6600’s CPU is sometimes described as having “long add” because the 18-bit increment units are also adders)
  6. Floating-point Divide unit – one copy; 2 900 ns latency
  7. Floating-point Multiply unit – two copies (parallel multiplication for matrix work)
  8. Increment unit – two copies; 18-bit fixed-point operations on address registers, also used for memory load/store completion

Several sources count the population-count instruction by where it executes (in the divide unit), so the canonical “10” includes the two multiplies and the two increment units. Wikipedia’s current table writes the list as “branch, boolean, shift, long integer add, floating point add, floating point multiply (two), floating point divide, incrementers (two; also performed memory operations)” – which is the same list.

The Scoreboard

  • The hardware unit that orchestrated functional-unit dispatch is called the Scoreboard (Cray’s name; Thornton, in his 1970 book, calls it the “Unit and Register Reservation Control”). [Thornton 1970; gunkies.org CDC 6600 wiki]
  • Functional unit dispatch was dynamic and out-of-order: the scoreboard issued an instruction as soon as its operands and a target functional unit were available, regardless of program order, then resolved write-back order to maintain semantic correctness.
  • The scoreboard handled three dependency classes (per the HASE Edinburgh model):
    1. First-order conflicts: target functional unit or destination register busy
    2. Second-order conflicts (Read-After-Write): instruction needs an operand that an earlier instruction has not yet written
    3. Third-order conflicts (Write-After-Read): instruction’s destination register has a pending read from an earlier instruction
  • This is the first commercial implementation of dynamic instruction issue with hardware dependency tracking. Tomasulo’s algorithm at IBM (System/360 Model 91, 1967) is sometimes cited as the first; it was actually three years later. The 6600 scoreboard predates Tomasulo by three years. [Standard architectural histories; Hennessy and Patterson]
  • Minor cycle (CPU clock): 100 ns nominal. The CPU could issue one instruction per minor cycle and dispatch to whichever functional unit was free; multiple instructions could be in-flight simultaneously across the units. [Wikipedia; HASE 6600; Thornton]

Instruction stack

  • The CPU also had an instruction stack of eight 60-bit registers (the “instruction buffer” or “I-stack”). It functioned as a small loop cache: when a backward branch returned to an instruction whose word was already in the stack, the loop body executed without re-fetching from memory. [HASE 6600; Thornton]

Peripheral Processor Units (Barrel)

The PPU subsystem is the most often-cited architectural innovation of the 6600 after the parallel functional units. It is the original “barrel processor.”

  • Ten Peripheral Processors (PPs). Each is a complete 12-bit computer, with 4 096 12-bit words of magnetic-core memory of its own. [Wikipedia: CDC 6600; HandWiki]
  • Implementation: virtual. There is only one physical PP datapath. The single physical processor cycles through ten register banks, presenting a different “PP” to the rest of the machine on each minor cycle. From outside, the system sees ten independent 12-bit computers running in parallel. From inside, one physical processor time-slices among them at 100-ns granularity. [Wikipedia; chessprogramming wiki]
  • Barrel rotation: 1 000 ns = ten PP states x 100 ns per state. Each PP therefore appears to run at one-tenth of the central CPU’s nominal clock rate, but receives 100 % of its dedicated cycle when its turn comes. [Wikipedia: CDC 6600]
  • Why? The central CPU is a hot, expensive resource. Tying it up servicing terminals, tape drives, card readers, line printers, and disk would waste it. Cray’s design lifted all of that onto the PPs. The CPU did pure floating-point arithmetic; the PPs handled file I/O, terminal traffic, scheduling, OS supervision, and dispatch. The CPU never executed an interrupt handler; it could not. [Thornton 1970; Wikipedia: Barrel processor]
  • The OS lived on PP0. The central operating system kernel ran on PP0; the other nine PPs handled I/O channels and user-process supervision. The CPU itself ran no OS code at all. This is the architectural inversion that distinguishes the 6600 from contemporary IBM systems. [Wikipedia: CDC 6600; Thornton]
  • Twelve I/O channels connected the PP subsystem to disks, tapes, card readers, printers, and the operator console. [Thornton; Wikipedia]
  • Population count and CRT console. The 6600’s operator console used a built-in cathode-ray-tube (CRT) display – the first commercial computer to do so. The display was driven by a PP, not by the CPU. [Wikipedia: CDC 6600]

The barrel idea – significance

The barrel processor pattern was reused: in the CDC 7600, 8600, in early Tera/MTA machines, and (philosophically) in modern simultaneous-multithreaded (SMT, hyper-threaded) processors. The 6600 PP subsystem is the first commercial implementation of the barrel pattern, and the first known case of running an entire OS on a coprocessor while reserving the main CPU for compute. [Wikipedia: Barrel processor]

Memory

  • Magnetic-core memory. [Wikipedia: CDC 6600; chessprogramming wiki]
  • Basic configuration: 32 768 60-bit words (often written 32K) of central memory. [Wikipedia / Thornton common base config; Museum Waalsdorp]
  • Maximum configuration: 131 072 60-bit words (often written 128K) – about 982 kilobytes. [Wikipedia; chessprogramming wiki; gunkies CDC 6600 wiki]
  • NCAR’s 6600 had 65 536 words (“65 000 60-bit words”), a mid-range configuration. [NCAR/CISL]
  • Memory cycle time: 1.0 microsecond. [Museum Waalsdorp; gunkies CDC 6600 wiki]
  • Bank interleaving: 8-way. The central memory was split into eight banks accessible in parallel; with the CPU minor cycle at 100 ns, eight-way interleaving was needed to feed the CPU at full rate. [Museum Waalsdorp]
  • No parity, no byte-addressability. Character handling required shift and mask. Six-bit characters (CDC display code) packed ten to a 60-bit word. [Museum Waalsdorp]
  • Extended Core Storage (ECS). An optional second-tier memory, accessible only via block move, with 3.2-microsecond cycle time and 24-bit addressing. [Museum Waalsdorp]

Performance

  • Peak compute rate: ~3 MFLOPS (3 million floating-point operations per second). Often quoted as the marketing figure: “3 MIPS, 3 MFLOPS, 10 MHz.” [CHM Revolution: “executed a dizzying 3 000 000 instructions per second”; Wikipedia; Thornton]
  • FORTRAN-realised performance: typically 0.5–1 MFLOPS depending on compiler and code. The peak number assumed perfect functional-unit utilization. [Wikipedia: “FORTRAN reality ~0.5 MFLOPS with best compilers”]
  • CPU minor cycle: 100 ns = nominal 10 MHz CPU clock. [Wikipedia; chessprogramming wiki]
  • Memory cycle: 1.0 microsecond. [Museum Waalsdorp; gunkies CDC 6600 wiki]
  • Comparison to the IBM 7030 Stretch. Wikipedia’s CDC 6600 article and the Wikipedia 7030 Stretch article both state the 6600 was “almost three times faster” than Stretch. Stretch had been IBM’s flagship supercomputer of the early 1960s, having been originally promised at 100x the IBM 704 and delivered at about 30x; IBM took it off the price list after the disappointing benchmarks. The 6600’s three-times-Stretch figure is the canonical “the 6600 is three times the previous fastest computer.” [Wikipedia: CDC 6600 and IBM 7030; Murray]
  • Comparison to the IBM 7090. CERN’s documentation states the 6600 had “about 10 times the processing capacity of the IBM 7090” – a useful figure because the 7090 was IBM’s mainstream scientific machine in the early 1960s, in service at NWP centres, NASA, and most of the major universities. [CERN Timeline; HPCwire 2014 CERN history article]

Logic Technology and Cordwood Modules

  • Approximately 400 000 transistors per system. [Wikipedia: CDC 6600; CHM Revolution; Murray]
  • Silicon transistors, not germanium – the 6600 was the first CDC machine to use silicon throughout. The 1604 had been germanium. The transition reflects both the maturation of silicon manufacturing in 1961–1963 and Cray’s deliberate bet on the faster silicon switching time. [Wikipedia: CDC 6600; CHM transistor history]
  • About 6 000 cordwood modules per system. [Wikipedia: CDC 6600]
  • Cordwood module dimensions: ~64 mm (2.5 inches) square, ~25 mm (1 inch) thick. A 30-pin connector on one edge (two rows of 15), six test points on the opposite edge, ~64 silicon transistors per module mounted “cordwood” style (densely between two parallel printed-circuit cards). [Wikipedia: CDC 6600]
  • Module library: roughly 100 distinct types. Cray’s design philosophy was to use a small set of module types in many places, simplifying manufacturing and field replacement. [Multiple secondary sources]
  • Wiring: over 100 miles of hand-wired connections per machine. [The Register, 2007; CHM Revolution]
  • Logic family: direct-coupled transistor logic (DCTL). [Museum Waalsdorp]
  • Estimated MTBF: over 2 000 hours based on transistor reliability metrics of the early 1960s – a substantial improvement over the 1604 (germanium DTL) and an enormous improvement over the IBM 7090 (transistor) and IBM 7094. [Museum Waalsdorp]

Freon Cooling

The 6600 was the first commercial computer where forced-Freon refrigeration was the primary cooling system. The component density was too high for forced-air cooling at the heat output of the silicon-transistor cordwood modules.

  • Cabinet shape: a plus sign (“+”-shaped) with four arms radiating from a central column. The CPU mainframe occupied the central column and the inner portion of each arm; modules and chassis were arranged for short, regular wire runs. [Wikipedia: CDC 6600]
  • The outermost 18 inches (46 cm) of each of the four arms held the refrigeration plenum: a Freon pump and a Freon-to-water heat exchanger. [Wikipedia: CDC 6600]
  • Cooling cycle. Liquid Freon circulated within the cabinet, absorbed heat from the cordwood modules through metal cold plates pressed against the module fronts, then surrendered that heat at the heat exchangers in the cabinet plenum to an external chilled-water supply that ran through the building. The refrigeration was inside the machine cabinet; the chilled-water plant was a building-services responsibility. [Wikipedia: CDC 6600; CHM Revolution: “Metal plates in contact with circulating Freon cooled the cordwood modules”]
  • Why Freon? Forced air at the heat density of silicon-transistor cordwood modules at 100-ns clock rate was insufficient. Freon (chlorofluorocarbon refrigerant; specifically, the 6600 used variants of R-12 as standard at the time) had high latent heat of vaporization, low boiling point, and was non-toxic and non-flammable in normal use. Forced-Freon refrigeration had been used in special-purpose military computers (some IBM AN/FSQ-7 SAGE installations) but not in a commercial scientific computer.
  • Freon-leak anecdotes (low confidence on details). Multiple secondary accounts describe Freon-leak incidents during the 6600 production years, both at Chippewa Falls during prototype assembly and in the field at customer sites. The Murray Supermen book is reportedly the canonical source for these stories; one I have not verified but have seen cited involves a leak that vented Freon into the lab and necessitated evacuation. Flag as anecdote; verify against Murray before using.
  • Weight and physical scale. ~12 000 lb (5.4 tonnes) for the central CPU cabinet. CPU cabinet alone was approximately 68 inches wide, 79.5 inches high, 32 inches deep (172.7 x 201.9 x 81.3 cm). [CHM catalog X1385.97F]

Cost and Sales

Price

The price figures in the literature vary depending on whether the cited price is per central processor cabinet, basic system, full configuration, or full installation including peripherals. The figures I have found:

  • CHM catalog X1385.97F (Livermore unit, 1964): $7 000 000. This is the authoritative museum price for the first delivered system. [CHM Catalog]
  • The Register (2007): “$6–10 million each.” [The Register, 2007]
  • Murray’s The Supermen (per HPCwire review, 1997): “around $8 million each.” [HPCwire 1997 review of Murray]
  • Wikipedia’s infobox: $2 370 000 (equivalent to ~$24.6M in 2025). This figure is consistently the lowest cited; it likely refers to a stripped-down configuration or central-processor cabinet alone. Wikipedia’s number is anomalous; the secondary literature converges on $7–10 million. [Wikipedia: CDC 6600]

Use $7–10 million per system in 1964 dollars as the safe, well-sourced range. $8 million is a reasonable single-figure quote if a single number is needed.

Sales

  • About 100 systems sold over the production run. [Wikipedia: CDC 6600; Murray; CHM Revolution: “Control Data sold approximately 100 units”]
  • Production years: roughly 1964–1972 (some 6000-series production continued longer with the 6700 and Cyber-series successors).
  • The 6600 was the most commercially successful supercomputer-class machine of its era. By comparison: IBM 7030 Stretch (9 sold, then withdrawn); UNIVAC LARC (2 sold); Atlas (3 sold). The 6600 was the first machine in its class to achieve a production-scale customer base.

Software (SCOPE, KRONOS, FORTRAN)

  • COS (Chippewa Operating System): the original, simple job-control system that ran on PP0. Named for the development location.
  • SCOPE (Supervisory Control Of Program Execution): CDC’s official, batch-oriented operating system for the 6600. Evolved from COS. SCOPE 3.0 was the standard production OS at most customer sites. [Wikipedia: CDC 6000 series]
  • KRONOS (Greek god of time): introduced ~1970. A time-sharing-oriented operating system, alternative to SCOPE for academic and university customers. KRONOS later evolved into NOS (Network Operating System) and NOS/BE for the Cyber-series successors. [Wikipedia: CDC 6000 series]
  • MACE: an enhanced version of COS, built at Lawrence Livermore. Influenced the later development of NOS.
  • Third-party operating systems existed: NCAR famously developed its own operating system, having found CDC’s SCOPE inadequate for atmospheric-science workflows. The NCAR system was developed in part on a 6600 simulator running on NCAR’s CDC 3600. [NCAR/CISL]
  • FORTRAN. CDC supplied a FORTRAN compiler (“RUN” was the initial CDC FORTRAN; later FTN, MNF) tuned for the parallel functional units. The compiler’s ability to schedule instructions across the multiple functional units was a major selling point and a non-trivial technical achievement. The 6600 was where compiler-driven instruction scheduling for parallel functional units became a practical engineering problem. [Wikipedia: CDC 6000 series; Thornton 1970]
  • COMPASS: the 6600 assembly language. [Wikipedia: CDC 6600; gunkies wiki]

The Instruction Set as RISC Ancestor

The 6600’s instruction set is one of the canonical historical ancestors of RISC. The lineage is well-documented:

  • Cray’s deliberate design choice: a small, regular, register-based instruction set with simple addressing modes (register+register, register+immediate – the load-store discipline of modern RISC), one-cycle dispatch from the issue unit, and dedicated separate units for each operation type. The reasoning was practical: a small instruction set meant a fast scoreboard could keep up with the CPU’s 100 ns minor cycle. Complexity in the issue and dependency-tracking logic was a hard limit on clock speed. [Thornton 1970]
  • 74 operation codes – comparable to the early Berkeley RISC-I (~30) and Stanford MIPS (~50) prototypes of the early 1980s. [Wikipedia: RISC; Museum Waalsdorp]
  • Two addressing modes only, register+register and register+immediate – the canonical RISC characterization. [Wikipedia: RISC]
  • Patterson 1985, “Reduced Instruction Set Computers” (CACM, January 1985): David Patterson’s canonical RISC paper. The 6600 is referenced as historical antecedent. [Patterson, CACM 28(1):8–21, January 1985 – I have not been able to read the article behind the paywall, but the citation chain to Patterson 1985 is repeatedly made in subsequent textbook references.]
  • Hennessy and Patterson, Computer Architecture: A Quantitative Approach (1990 first edition, multiple subsequent editions): the standard graduate textbook. The 6600 is treated explicitly as a RISC architectural ancestor; the scoreboard chapter uses the 6600 as the worked example for dynamic out-of-order issue.
  • Jack Dongarra’s quoted assessment (per Wikipedia: RISC article): “Partly due to the optimized load–store architecture of the CDC 6600, … it can be considered a forerunner of modern RISC systems, although a number of other technical barriers needed to be overcome for the development of a modern RISC system.” [Wikipedia: RISC, citing Dongarra]
  • Cray’s instruction set was load–store: arithmetic happened only in registers; memory access happened only via the address-register dance (load A1–A5 with an address to trigger an automatic load into the corresponding X register; load A6 or A7 to trigger a store). This “loads and stores are the only memory ops” rule is what makes the 6600 a load-store architecture.

The 6600 is therefore both the first commercial supercomputer AND the first machine whose architectural philosophy is recognizable as proto-RISC. The two facts are connected: Cray’s pursuit of speed forced him toward a minimal, regular instruction set with hardware dependency tracking – which is exactly the philosophy that the Berkeley and Stanford RISC projects rediscovered fifteen years later.

Major Customers

The 6600’s customer list reads as a who’s-who of mid-1960s big-science computing.

National laboratories (early customers, 1964–1965)

  • Lawrence Livermore National Laboratory – first delivery, September 1964. The CHM CPU cabinet (X1385.97F) is from this Livermore unit. Used for nuclear-weapons hydrodynamics simulation, the Lab’s mainstream classified workload. [CHM Catalog; Wikipedia: CDC 6600]
  • Los Alamos National Laboratory – 1965. Nuclear-weapons design. [Wikipedia: CDC 6600]
  • Lawrence Berkeley National Laboratory – mid-1960s. High-energy-physics analysis. [Wikipedia: CDC 6600]

National Security Agency

  • NSA acquired multiple 6600s during the 1960s for cryptanalytic work. Cray’s relationship with NSA dated to his ERA / UNIVAC 1103 days; the 6600’s population-count instruction is repeatedly cited as a feature added at NSA’s request. NSA used 6600s and the related CDC 6400 for ELINT processing during the Vietnam War. [NSA “Seymour Cray” pamphlet, 5 October 2018; Wikipedia: Seymour Cray]

CERN

  • CERN, Geneva – delivered 14 January 1965, serial number 3 (a pre-production model). Used for analysing the 2–3 million bubble-chamber-track photographs CERN produced annually. CERN’s previous main computer was an IBM 7090; the 6600 offered roughly ten times the throughput. The first multi-programmed machine in the CERN Computer Centre. CERN’s 6600 ran from 1965 until 1975 (with a two-month shutdown in 1968 for major hardware modifications). [CERN Timeline; HPCwire 2014]
  • CERN’s 6600 is the first European supercomputer-class machine.

NCAR

  • NCAR (National Center for Atmospheric Research, Boulder) – serial number 7, delivered December 1965. Initially installed in a University of Colorado building because the Mesa Lab was still under construction; moved to the Mesa Lab in December 1966. Configuration: 65 536 60-bit words of memory; 10 MHz clock. Decommissioned May 1977 after eleven years of service. NCAR’s CDC 3600 (delivered November 1963) had been the institution’s first computer; the 6600 supplemented and then succeeded it. [NCAR/CISL: “CDC 6600”]
  • Critical NWP context: the NCAR 6600 was not commissioned until December 1965, and the Mesa Lab move happened a year later. The first published NCAR Global Circulation Model (Kasahara and Washington, Monthly Weather Review, July 1967) was developed and run on this machine. [NCAR/CISL; Kasahara & Washington 1967, Mon. Wea. Rev. 95:389–402]

Other customers

  • NASA Goddard – mid-1960s. [Multiple secondary sources]
  • MIT Lincoln Laboratory – mid-1960s. Radar / signal-processing research.
  • Courant Institute of Mathematical Sciences (NYU). [Wikipedia: CDC 6600]
  • Several European universities and meteorological services – low-confidence on specific lists; will need to verify per case.

The full sales of ~100 6600s spread across roughly: ~30 to U.S. weapons labs and DoD agencies, ~15 to NASA and Air Force research, ~20 to U.S. universities, ~25 to international customers (CERN being the headline), ~10 commercial. These percentages are rough estimates from secondary sources; flag as low-confidence aggregation.

NWP and Atmospheric Science Use

The 6600 is the machine on which the modern atmospheric general-circulation model emerged at NCAR.

NCAR and the Kasahara–Washington GCM

  • Akira Kasahara and Warren Washington began NCAR’s GCM project in 1964, when the NCAR computing facility ran the CDC 3600. The 6600 arrived in December 1965 and provided the computing power that made full general-circulation simulation practicable. [NCAR/UCAR News: “Atmosphere in a box”; NCAR/CISL CDC 6600 page]
  • First publication: Kasahara, A. and W.M. Washington, 1967: “NCAR Global General Circulation Model of the Atmosphere,” Monthly Weather Review, 95(7), 389–402. A simple two-layer global model with 5-degree horizontal resolution. The vertical coordinate was height (not pressure, the choice everyone else was making at the time); hydrostatic equilibrium was maintained.
  • Continued development on the 6600 through 1970–1973. Higher-resolution and more vertical layers were progressively added as the model grew. The 6600 served the GCM until the CDC 7600 arrived in May 1971; the 6600 then continued in service for additional simulation work, batch processing, and graphics rendering until decommissioning in May 1977. [NCAR/CISL CDC 6600; NCAR/CISL CDC 7600]
  • Akira Kasahara himself: see post 22 (the “fireman and the visionary” post on Arakawa) for the broader NCAR / GCM context. Kasahara was Japanese-born, came to NCAR in 1963 after a postdoc at MIT under Charney’s supervision and a stint at the University of Chicago, and led NCAR’s atmospheric modelling effort with Washington for decades.

CERN – not weather

  • CERN’s 6600 was used for high-energy physics, not weather. It analyzed bubble-chamber photographs from the PS, the ISR, and (later) SPS experiments. The CDC 6600 has no role in CERN’s weather work because CERN had none. [CERN Timeline]

European weather services

  • The European meteorological centres of the late 1960s – the UK Meteorological Office, Deutscher Wetterdienst, Meteo France, the Swedish SMHI – generally did not buy CDC 6600s for operational forecasting. They were IBM 7090 / IBM 360 customers in the 1960s and turned to CDC and Cray only later (the 7600 era and after). The 6600 thus belongs in the NWP story as a research-NWP machine at NCAR and (later) in some European university groups, not as an operational forecasting platform.
  • A possible exception: I have not been able to confirm whether any operational forecasting service used a 6600 for production runs. Flag as open question.

U.S. National Weather Service / NMC at Suitland

  • The National Meteorological Center / NWS at Suitland, Maryland was an IBM shop in the 6600 era: IBM 7094 (1962) -> IBM 360/195 (1971) -> Cyber 7600 / Cyber 205 in 1979. The 6600 was not in operational use at NMC. The civilian operational NWP centre’s first CDC machine was the Cyber 7600 in 1979. [NCEP / NMC institutional histories]
  • Fleet Numerical Weather Facility (FNWF / FNMOC) at Monterey continued on its CDC 1604s and CDC 3000-series machines into the late 1960s before transitioning to the IBM 360/67 (1967) and CDC 6500 (1970). I have not found a confirmed FNWF 6600 acquisition.

Successors: 6700, 6800 (cancelled), 7600

The clean lineage to quote is 6600 (1964) -> 7600 (1969) -> Cray-1 (1976), with the 6700 as a contemporary variant and the 6800 as the cancelled-project that drove Cray to leave CDC.

CDC 6700 (1969–1971)

  • A hybrid dual-CPU system: one 6600 central processor and one 6400 (lower-cost, sequential) central processor sharing memory. [Wikipedia: CDC 6000 series]
  • Marketed to customers who needed a 6600’s compute power for batch jobs but a cheaper 6400 to handle interactive time-sharing.
  • A relatively low-volume product compared to the 6600 itself.

CDC 6800 – the cancelled successor

  • The 6800 was a Cray-led successor design intended to be the next-generation CDC supercomputer after the 6600. Begun ~1968 at Chippewa Falls.
  • Cancelled by CDC management around 1972. This cancellation was the immediate precipitant for Cray’s departure: Norris had previously backed Cray’s projects, but by the early 1970s CDC was consolidating around the Cyber series and the 7600, and the company chose not to fund the 6800 further.
  • Cray left CDC in 1972 to found Cray Research. Norris reportedly invested $250 000 in startup capital and – in a famous exchange – asked Cray for a five-year plan; Cray’s reply was a short note: “Five-year goal: Build the biggest computer in the world. One-year goal: One-fifth of the above.” [Wikipedia: Seymour Cray; Murray]
  • There was also a CDC 8600 project that Cray began at Cray Research and abandoned. Sources sometimes conflate the 6800 (CDC) and 8600 (Cray Research / CDC); they were distinct projects, with the 6800 being earlier and the 8600 being the brute-force four-CPU design that Cray gave up on after the Cray-1’s success in 1976. The 6800 / 8600 distinction is sometimes blurred in secondary sources – flag for careful citation.

CDC 7600 (1969)

  • Cray’s pipelined follow-on at CDC. Announced June 1967, first delivered 1969. [Wikipedia: CDC 7600]
  • Architecture: pipelined functional units. Where the 6600 had ten parallel functional units that each had to complete before accepting the next instruction, the 7600 broke each functional unit into stages so that successive instructions could enter the pipeline before the previous one finished. The 7600 thus added pipelining on top of the 6600’s parallelism.
  • Performance: about 10x the 6600 on hand-tuned code. Peak ~36 MFLOPS, sustained ~10 MFLOPS. [NCAR/CISL CDC 7600]
  • Iconic C-shaped chassis to minimize signal-travel distance – the visual signature later inherited by the Cray-1.
  • NCAR took serial number 12, delivered 24 May 1971 (NCAR/CISL gives 3 May; HandWiki gives 24 May – minor date discrepancy in secondary sources, but May 1971 is firm). It served NCAR until 1983. The 7600 was the immediate predecessor to the Cray-1 at NCAR (Cray-1 serial #3, July 1977, $8.86M). [NCAR/CISL: CDC 7600 and Cray-1 pages]
  • Reliability: both LLNL and NCAR reported the 7600 broke down at least once a day, often four or five times. [NCAR/CISL CDC 7600]
  • The 7600 is the bridge between the 6600 and Cray’s eventual departure from CDC; it was the last CDC machine Cray fully designed.

Anecdotes

Watson Jr.’s 28 August 1963 memo (THE iconic anecdote)

The single most-quoted internal memo in computer-industry history, written by IBM’s Tom Watson Jr. on 28 August 1963, the same day CDC publicly announced the 6600. The verbatim text:

“Last week CDC had a press conference during which they officially announced their 6600 system. I understand that in the laboratory developing this system there are only 34 people, ‘including the janitor.’ Of these, 14 are engineers and 4 are programmers, and only one person has a Ph.D., a relatively junior programmer. To the outsider, the laboratory appearing to be receiving any sustaining support is a small one in Chippewa Falls. Contrasting this modest effort with our vast development activities, I fail to understand why we have lost our industry leadership position by letting someone else offer the world’s most powerful computer.”

[Watson memo, 28 August 1963; CHM Revolution: “Watson Jr. memo about CDC 6600”; reproduced in Murray; quoted on Hacker News and HPC blogs widely.]

Cray’s reply, on being told of the memo: “It seems like Mr. Watson has answered his own question.” [Multiple secondary sources, including hpcdan.org “Memos, Janitors, Teams, and Innovation,” 2022; HandWiki: CDC 6600]

The phrase “including the janitor” became shorthand for the small-team-out-engineers-the-giant principle in the computing industry. It is the moment IBM publicly recognized that something fundamental had changed about how to build a fast computer.

Cray as design tool: pencil and graph paper

  • Cray designed the 6600 – like every machine before and after – with #3 Ticonderoga pencils and graph paper, no CAD. He suggested using the back of the graph paper “so the lines weren’t too bright.” [Murray; NSA “Seymour Cray” pamphlet 2018]
  • His desk was famously empty: workbook and a pencil, both lined up parallel.
  • Status reports were minimal. One Cray monthly summary read in its entirety: “Activity is progressing satisfactorily as outlined under the June plan. There have been no significant changes or deviations from the June plan.”

Norris and the Chippewa Falls bargain

Norris’s decision to back Cray’s demand for the Chippewa Falls lab in 1962 – against advice from the rest of CDC management, which wanted Cray in Minneapolis – is a major institutional anecdote. It reflects Norris’s confidence in Cray and CDC’s then-emerging culture of letting its star engineer have the conditions he asked for. The same dynamic, ten years later, would not survive the 6800 cancellation, and Cray would leave CDC in 1972. The Chippewa Falls / Cray / Norris story is the spine of the company-as-character arc of the 6600 chapter. [Murray; The Register, 2007]

Freon-leak stories (low confidence on specifics)

Multiple secondary sources allude to Freon-leak incidents during 6600 production and field service. Murray’s The Supermen is reportedly the canonical source for these stories. I have not verified individual leak anecdotes against primary sources. Flag as anecdote; verify before using direct quotes.

“Like a master pianist”

Edward Norton Ward, the first computer technician at the Naval Postgraduate School (where Cray had personally installed the 1604 in January 1960), recalled Cray during installation as “like a master pianist,” running through test programs by hand. The same description echoes in 6600-era accounts of Cray walking onto a customer floor for an installation. [CHM “Weather by Computer” 1604 brochure period]

Engineering at Chippewa Falls

  • The Chippewa Falls laboratory operated as a small, quiet, secluded engineering shop. No corporate visitors, no marketing department dropping in, no Minneapolis bureaucracy. Cray protected the team’s working conditions fiercely.
  • Long hours during the prototype assembly (1962–1963). Multiple secondary sources describe Cray and Thornton spending evenings and weekends in the lab.
  • The team had its own canteen and a small stockroom, with module replacements stored in a cabinet in the corner.
  • Population-count-instruction story: NSA cryptanalysts visited Chippewa Falls during the 6600 design phase, and the population-count opcode was added to the spec at their request. The instruction was implemented in the divide unit, sharing hardware with floating-point divide – an elegant Thornton solution. [Multiple secondary sources; NSA pamphlet 2018]

Sources

Primary

  • Thornton, James E. Design of a Computer: The Control Data 6600. Glenview, Illinois: Scott, Foresman, 1970. THE primary technical reference, written by the 6600’s principal hardware architect. Computer History Museum scan: https://archive.computerhistory.org/resources/text/CDC/cdc.6600.thornton.design_of_a_computer_the_control_data_6600.1970.102630394.pdf – and Internet Archive: https://archive.org/details/CDC6600Thornton

Secondary – canonical popular history

  • Murray, Charles J. The Supermen: The Story of Seymour Cray and the Technical Wizards Behind the Supercomputer. New York: John Wiley & Sons, 1997. ISBN 978-0471048855. The canonical popular history of CDC and Cray. Verify the freon-leak anecdotes, the 37-cent-transistor anecdote (which belongs to the 1604 era), and the small-team-at-Chippewa-Falls accounts against this volume’s specific pages before quoting verbatim.
  • HPCwire review of The Supermen by Anonymous, 21 February 1997: https://www.hpcwire.com/1997/02/21/review-how-supercomputing-started-plus-a-bit-more-the-supermen-the-story-of-seymour-cray-and-the-technical-wizards-behind-the-supercomputer-by-charles-j-murray/

RISC ancestry

  • Patterson, David A. “Reduced Instruction Set Computers.” Communications of the ACM 28(1): 8–21, January 1985. https://cacm.acm.org/research/reduced-instruction-set-computers/ The canonical RISC paper. The CDC 6600 is referenced as architectural antecedent.
  • Hennessy, John L. and David A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 1990 (1st edition); multiple subsequent editions. The 6600 is the canonical worked example for dynamic instruction issue in the scoreboarding chapter, and is treated as a RISC architectural ancestor in the historical perspective sections.
  • Patterson, David A. and Carlo H. Sequin. “RISC I: A Reduced Instruction Set VLSI Computer.” Proc. 8th International Symposium on Computer Architecture (ISCA), Minneapolis, May 1981, pp. 443–457. The Berkeley RISC-I paper, where the 6600’s load-store architecture is part of the historical motivation.
  • Patterson, D.A. and D.R. Ditzel. “The Case for the Reduced Instruction Set Computer.” ACM SIGARCH Computer Architecture News 8(6):25–33, October 1980. https://people.eecs.berkeley.edu/~kubitron/courses/cs252-F00/handouts/papers/patterson80.pdf The first proposal of the RISC name and concept, which references the 6600 as a precedent.

Online encyclopedia and museum sources

  • “CDC 6600,” English Wikipedia: https://en.wikipedia.org/wiki/CDC_6600
  • “CDC 6000 series,” English Wikipedia: https://en.wikipedia.org/wiki/CDC_6000_series
  • “CDC 7600,” English Wikipedia: https://en.wikipedia.org/wiki/CDC_7600
  • “Seymour Cray,” English Wikipedia: https://en.wikipedia.org/wiki/Seymour_Cray
  • “Reduced instruction set computer,” English Wikipedia: https://en.wikipedia.org/wiki/Reduced_instruction_set_computer
  • “Barrel processor,” English Wikipedia: https://en.wikipedia.org/wiki/Barrel_processor
  • “IBM 7030 Stretch,” English Wikipedia: https://en.wikipedia.org/wiki/IBM_7030_Stretch
  • “CDC 6600,” Grokipedia: https://grokipedia.com/page/CDC_6600
  • “CDC 6600,” HandWiki: https://handwiki.org/wiki/CDC_6600
  • “CDC 6600,” Computer History Wiki (gunkies.org): https://gunkies.org/wiki/CDC_6600
  • “CDC 6600,” Chessprogramming wiki: https://www.chessprogramming.org/CDC_6600

Computer History Museum

  • “CDC 6600’s Five Year Reign,” CHM Revolution: https://www.computerhistory.org/revolution/supercomputers/10/33
  • “CDC 6600 CPU cabinet (1 of 4),” CHM Catalog X1385.97F (Livermore unit): https://www.computerhistory.org/collections/catalog/X1385.97F
  • “Watson Jr. memo about CDC 6600,” CHM Revolution: https://www.computerhistory.org/revolution/supercomputers/10/33/62

NCAR / atmospheric science

  • “CDC 6600,” NCAR/CISL Supercomputing History: https://www.cisl.ucar.edu/ncar-supercomputing-history/cdc6600
  • “CDC 7600,” NCAR/CISL Supercomputing History: https://www.cisl.ucar.edu/ncar-supercomputing-history/cdc7600
  • Kasahara, A. and W.M. Washington. “NCAR Global General Circulation Model of the Atmosphere.” Monthly Weather Review, 95(7):389–402, July 1967. https://journals.ametsoc.org/view/journals/mwre/95/7/1520-0493_1967_095_0389_nggcmo_2_3_co_2.xml
  • “Atmosphere in a box: NCAR’s first GCM,” UCAR News: https://news.ucar.edu/3256/atmosphere-box-ncars-first-gcm
  • “NCAR and UCAR mourn the passing of pioneering scientist Akira Kasahara,” UCAR News (Kasahara obituary): https://news.ucar.edu/132834/ncar-and-ucar-mourn-passing-pioneering-scientist-akira-kasahara

CERN

  • “CDC 6600 arrives at CERN,” CERN Timeline: https://timeline.web.cern.ch/cdc-6600-arrives-cern
  • “Window in time opens up CERN’s supercomputing history,” HPCwire, 14 January 2014: https://www.hpcwire.com/2014/01/14/window-time-opens-cerns-supercomputing-history/

Architectural detail

  • “The CDC 6600 Architecture” (educational page): http://ygdes.com/CDC/cdc6600.html
  • “CDC 6600 Simulation Model,” HASE, University of Edinburgh: https://www.icsa.inf.ed.ac.uk/research/groups/hase/models/6600/index.html
  • “Computer history: CDC 6000 Series Hardware Architecture,” Museum Waalsdorp: https://www.museumwaalsdorp.nl/en/history/computerhistory-background-information/6400hwac/

Watson memo and Cray reply

  • “Memos, Janitors, Teams, and Innovation,” Reed’s Ruminations (Dan Reed), 22 February 2022: https://hpcdan.org/2022/02/22/memos-janitors-teams-and-innovation/
  • “Remembering the CDC 6600,” The Register, 3 December 2007: https://www.theregister.com/2007/12/03/tob_cdc_6600/

NSA

  • “Seymour Cray and NSA,” NSA declassified pamphlet, 5 October 2018: https://www.nsa.gov/portals/75/documents/news-features/declassified-documents/history-today-articles/10%202018/05OCT2018%20SEYMOUR%20CRAY%20and%20NSA.pdf

Cray corporate history

  • “Seymour Cray, History of Supercomputers,” Cray Inc.: https://www.cray.com/company/history/seymour-cray

Confidence flags

HIGH confidence (multiple primary or near-primary sources agree):

  • 60-bit word, 32 768 base / 131 072 max central memory, 1 microsecond memory cycle, 100 ns CPU minor cycle (10 MHz nominal)
  • 24 user-visible registers (8 X 60-bit, 8 A 18-bit, 8 B 18-bit; B0 hardwired to zero)
  • Ten functional units (eight types, with multiply and increment duplicated)
  • Scoreboard for dynamic out-of-order issue (also called “Unit and Register Reservation Control” by Thornton)
  • Ten Peripheral Processors implemented as a single barrel processor cycling through 10 register banks at 100 ns per state, 1000 ns per full rotation
  • 12-bit PP word, 4 096 12-bit words of memory per PP
  • Approximately 400 000 silicon transistors, ~6 000 cordwood modules
  • Plus-shaped cabinet, Freon refrigeration with heat exchanger to building chilled-water supply
  • Public announcement 28 August 1963; first delivery to Lawrence Livermore September 1964
  • ~100 systems sold over 1964–1972 production run
  • CERN serial #3, 14 January 1965; NCAR serial #7, December 1965
  • Watson Jr.’s 28 August 1963 memo with the “34 people, including the janitor” line
  • Cray’s reply: “It seems like Mr. Watson has answered his own question”
  • 7600 (1969) was Cray’s pipelined follow-on at CDC; ~10x 6600 performance
  • Cray left CDC in 1972 after the 6800 was cancelled
  • The 6600 is widely cited (Patterson 1985, Hennessy and Patterson 1990 onward) as RISC architectural ancestor
  • NCAR’s Kasahara–Washington GCM ran on the NCAR 6600 from 1965 onward; first publication 1967

MEDIUM confidence (strong secondary sourcing but I’d want to double-check a primary source before quoting verbatim):

  • 74 operation codes – Wikipedia and Museum Waalsdorp agree, but the precise count varies slightly across sources
  • Population-count instruction added at NSA’s request – repeatedly cited in secondary sources, but I have not confirmed it against a primary NSA source
  • Module library of “approximately 100 distinct types”
  • Watson memo’s full text including the “14 engineers, 4 programmers, only one person with a Ph.D.” breakdown – I have used the version that appears in CHM and on hpcdan.org, but small wording differences exist between published copies
  • The “$7–10 million per system” price range – Wikipedia infobox says $2.37M, CHM says $7M for the Livermore unit, secondary sources say $7–10M; the $7–10M range is what I’d use, but the reconciliation against an authoritative price-list document would strengthen the citation

LOW confidence (treat as anecdote or open question):

  • Specific Freon-leak incidents during 6600 production and field service – alluded to in multiple secondary sources, but I have not verified individual stories against Murray’s The Supermen directly
  • The exact distribution of the ~100 6600 units across customer types (national labs, NASA, universities, international, commercial) – my “30/15/20/25/10” estimate is a rough secondary-source aggregation
  • The dating of the CDC 6800 vs. 8600 and which one Cray was working on at the time of his 1972 departure – secondary sources sometimes conflate the two
  • The Wikipedia $2 370 000 price figure – anomalous against the wider literature; either a per-cabinet price or a stripped-down config price; the secondary literature ($7–10M per system) is what I’d defer to

Note on the post arc

The 6600 sits at a hinge of the NWP / HPC story:

  • It is the first commercial supercomputer, and so the answer to “when did Big Science computing become its own product category?”
  • It is the machine that triggered IBM’s recognition that the rules had changed (Watson memo).
  • It is the architecture that bridged 1960s mainframes and modern out-of-order RISC processors (scoreboarded multiple functional units, load-store ISA).
  • It is the machine on which NCAR’s first GCM was developed (Kasahara–Washington 1967), tying it directly to the NWP series the user is writing.
  • It is the direct predecessor of the Cray-1 lineage through the 7600 – and thus the architectural ancestor of every supercomputer through the early 1990s.

The post can build through architecture (parallel functional units; barrel PPUs; Freon cooling), people (Cray, Thornton, Watson Jr., Norris), money ($7–10M per system, ~100 sold), and consequences (RISC ancestry; the 7600 follow-on; the 6800 cancellation that drove Cray out of CDC). The Watson memo is the natural set-piece – the moment IBM, the giant, looked at a 34-person team in rural Wisconsin and said “what just happened to us.”